This invention relates generally to monolithic microwave integrated circuits and in particular to field effect transistor structures used for monolithic microwave integrated circuit switches.
As it is known in the art, r.f. switches are used in a variety of r.f. signal processing applications. As is also known, monolithic microwave integrated circuit technology has been developed to provide monolithic circuit components that is, amplifiers, switches and the like to process analog signals at high operating frequencies.
One of the most common active devices employed in monolithic microwave integrated circuits is the field effect transistor. The most common transistor type is the so-called MESFET (metal electrode semiconductor field effect transistor) which includes a metal Schottky barrier contact to a n-type semiconductor material, and ohmic source and drain electrode contacts. MESFETS are employed because they are readily integrated in integrated circuits particularly with so-called gallium arsenide integrated circuits, the preferred material for use in monolithic microwave integrated circuits. Also used in MMIC's is the so-called HEMT (high electron mobility transistor). HEMT's and psuedomorphic HEMT's use hetro structures of alternating layers of GaAs, AlGaAs and InGaAs, for example, in the active layer of the device to create quantum well structures and layers in which electron mobility is high.
In monolithic microwave integrated circuits, several switching circuit types are known. The first switching type so-called passive switches include series and shunt coupled field effect transistors which are operated in a resistive or passive mode. These elements commonly have source and drain electrodes interconnected to form series or shunt switching networks and have gate electrodes connected to gate bias voltages used as a control voltage to change the channel resistance between the source and the drain electrode. The gate bias voltage is switched between an on-state of the transistor and a pinch-off state of the transistor. In the first state of the transistor, the "on-state", a relatively low resistance between source and drain electrodes is provided whereas in the second state, "the off-state", a relatively high resistance between source and drain electrodes is provided. In actual practice, the characteristic of the field effect transistor in both the off-state and the on-state is more complicated than a simple high resistance and low resistance described. In the on-state, the field effect transistor at microwave frequencies is modelled as a series resistance-inductance circuit. The resistance in this circuit is the so-called on-state resistance of the channel and source and drain contact resistances, and the inductance of this circuit is a parasitic inductance resulting from the size of the FET. The presence of the inductance makes impedance matching in the on-state of the field effect transistor more difficult. When the FET is in an off-state, the FET is modelled between the source and drain electrodes as a series resistance-inductance capacitance circuit. It is desireable in this state that the capacitance be as small as possible to prevent coupling of the signal from the drain to source electrodes. The presence of the parasitic inductance effectively increases the capacitive susceptance, particularly in the shunt configuration which permits more energy to be coupled into the resistance and provides more loss in the off-state of the field effect transistor. The advantage of passive switches is that they are relatively broadband. This advantage is achieved, however, at the expense of relatively high insertion loss due to the aforementioned parasitics.
A second type of switch is the so-called active switch in which gate and drain biases are provided to field effect transistors arranged to provide switching circuits. This type of switching circuit has the advantage of providing gain to the signal. This advantage comes at the expense of increased circuit complexity and circuit fabrication complexity relatively moderate power handling and bandwidth capabilities.
One problem which is common to both types of switches is the relatively large size of the FETS employed in each of the switch implementations. Conventionally used switching FETS are MESFET's having a topography which has been adapted from active power FET designs. Although such a FET performs adequately as a switching FET, in general it has some drawbacks which have heretofore limited the ability of artisians to integrate these FETS into higher order passive switches. It would be desireable to provide higher order active switching implementations such as 1.times.4, 2.times.4, and 4.times.4 switches on a single integrated circuit. Generally, such higher order implementation are not feasible, unless individual chips are connected together in a hybrid type of arrangement.
The conventional field effect transistor 20, as shown in FIG. 1, includes a substrate 22 having a ground plane 21 disposed over a first surface thereof, and disposed over a second surface thereof, an optional buffer layer 23. Disposed over the optional buffer layer 23 is typically an epitaxially grown and etched mesa structure 25. The mesa structure 25 includes an active layer 24a which has an n-type dopant concentration typically in the range of 10.sup.16 to 10.sup.18 carriers per cubic centimeter and optional contact regions 24b which typically are highly doped n-type having a dopant concentration in excess of about 10.sup.18 carriers per cubic centimeter. Alternatively, ion implanted, etched and isolated active regions may also be used. In keeping with conventional power FET structure design, a plurality of gate fingers are disposed to make Schottky barrier contact with the active layer 24a, as shown for example in FIG. 1. The plurality of gate fingers are connected to a common gate bus 27, as also shown. The gate fingers are used to space source regions 28a, 28b from interdigitated drain regions 26a-26c as shown and to provide a plurality of parallel field effect transistor cells. The interdigitated drain regions are connected to a drain contact 26 as also shown, but the source regions 28a-28b must be connected to the common source electrode 28 through an airbridge or overlay structure 29a, 29b as depicted in FIG. 1B. It is the presence of the overlay structure 29a-29b as shown in FIG. 1 or other source overlay structures as also known to one of skill in the art which complicate the fabrication of such switching FETS.
In power FET designs, the gate fingers are connected in parallel to minimize gate resistance. This is an important consideration for a power FET, since an input signal is fed to the gate electrode, and a relatively high gate resistance would result in input signal attenuation, reduced gain and frequency cut off.
However, since no r.f. signals are coupled to the gate electrodes in passive switching applications, this consideration should not be important for passive switching FETS. Moreover, as also shown in FIG. 1, the interconnections for the gate fingers, the interdigitated drain fingers, and the source pads occur off the mesa portion of the chip. This arrangement is also required in high power MESFETS in order to provide requisite FET parameters in these applications such as breakdown voltages and low leakage currents. Accordingly, by using conventional power FET approaches for switching MESFETS, the presence of the parallel gate fingers, the source overlay structures, and interconnections of gate electrodes, drain electrodes, and source electrodes to common gate, drain, and source pads which are disposed off the mesa unnecessarily increase the size and hence, parasitics, complexity, and fabrication difficulties of FETS when used as passive switches. This in turn limits their r.f. performance capabilities and also limits the degree to which the structures may be easily integrated to form higher order passive switches such as 1.times.4, 2.times.2, and 2.times.4 switching implementations.